Decreasing device size and increasing device density has traditionally been a high priority for the manufacturing of integrated circuits. Optical lithography has been the driving force for device scaling. Conventional optical lithography is limited to about 80 nm pitch for single exposure patterning. While double and other multi-patterning processes can realize smaller pitch, these approaches are expensive and more complex.
Directed self-assembly (DSA), a technique which aligns self-assembling polymeric materials on a lithographically defined guide pattern, is a potential option for extending current optical lithography beyond its pitch and resolution limits. The self-assembling materials, for example, are block copolymers (BCPs) that consist of “A” homopolymer(s) covalently attached to “B” homopolymer(s), which are coated over a lithographically defined guide pattern on a semiconductor substrate. The lithographically defined guide pattern is a pre-pattern that is encoded with spatial chemical and/or topographical information and serves to direct the self-assembly process and the pattern formed by the self-assembling materials. Subsequently, by annealing the DSA polymers, the A polymer chains and the B polymer chains undergo phase separation to form an A polymer region and a B polymer region that are registered to the guide pattern. Then, by removing either the A polymer region or the B polymer region by wet chemical or plasma-etch techniques, a pattern is formed for transferring to the underlying substrate.
One approach of DSA is graphoepitaxy in which self-assembly is directed by topographical features that are formed overlying a semiconductor substrate. This technique is used, for example, to create contact holes or vias that can be subsequently filled with conductive material for forming electrical connections between two or more layers of the semiconductor substrate. In particular, the topographical features are formed overlying the semiconductor substrate using one or more photomasks that define mask features and conventional lithographic techniques to transfer the mask features to a photoresist layer that overlies the semiconductor substrate to form a patterned photoresist layer. The patterned photoresist layer is then selectively etched to form the topographical features as guide patterns that are configured as confinement wells. The confinement wells are filled with a BCP that is subsequently phase separated to form, for example, etchable cylinders or other etchable features that are each formed of either the A polymer region or the B polymer region of the BCP. The etchable cylinders, or other etchable features, are removed to form openings and define a pattern for etch transferring the openings to the underlying semiconductor substrate.
Unfortunately, current techniques for forming defining the layers within a microchip (contact(s), gate(s), fin(s), etc.) require a significant number of photomasks/photolayers, multiple exposures for lithography (i.e., LELELE), etch steps, wet clean steps, and deposition steps. As such, there is considerable cost and complexity associated with patterning each individual layer, directed self-assembly is considered a promising technology due to its ability to decrease cost and complexity and possibly eliminate additional photomask/photolayer steps.
Accordingly, it is desirable to provide methods for fabricating integrated circuits that may reduce, minimize, or eliminate the use of photomasks and/or simplify the lithographical process steps for forming graphoepitaxy DSA patterns. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.